This application claims the benefit of Korean Patent Application No. 2002-0034385, filed Jun. 19, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
The present invention relates to methods for fabricating semiconductor devices, and more particularly, to methods for fabricating interconnections for semiconductor devices.
As the integration density of integrated circuit devices continues to increase, the distance between semiconductor devices in the integrated circuit may continue to decrease. As a result, the contacts to the individual devices may also decrease in size, which may reduce the alignment margin tolerances for the photolithography processes that are used to form these contact regions. Contact failures may result.
Photolithography is widely used to form desired patterns in semiconductor fabrication processes. However, as the density of these patterns continues to increase, it may be difficult to form the desired pattern using photolithography.
One particular example is the formation of a bit line of an integrated circuit memory device, such as a Dynamic Random Access Memory (DRAM). For a design rule of 0.1 xcexcm, the bit line size may be about 100 nm, and the misalignment margin may be about 40 nm. In this environment, the size of a storage node contact should be about 40 nm, which may be difficult to form using conventional exposure and photolithography processes. Increasing the storage node contact size beyond about 40 nm may reduce the misalignment margin, and a short circuit may occur between the storage node contact plug and a bit line, which may cause device failure.
Self-aligned contact processes are known, which can provide minimum misalignment margin in the photolithography process. Storage node contacts have been formed using self-aligned contact processes. However, even these self-aligned processes may use photolithography steps. Accordingly, it may be desirable to provide methods of fabricating semiconductor devices, wherein small contact holes, such as storage node contact holes, may be formed while preserving a desired misalignment margin.
Some embodiments of the present invention fabricate a semiconductor device by forming a series of alternating first and second elongated regions on a substrate, and etching a plurality of elongated trenches that are nonparallel to and extend across the first and second elongated regions. Material is placed in the plurality of elongated trenches. Portions of the first and/or second elongated regions are removed between adjacent ones of the plurality of elongated trenches that contain material therein, to define contact holes. In some embodiments, conductive material is placed in at least some of the portions of the first and/or second elongated regions that are selectively removed. In other embodiments, holes are etched beneath at least some of the portions of the first and/or second elongated regions that are selectively removed, and conductive material is placed in at least some of the portions of the first and/or second elongated regions that are selectively removed and in the holes beneath these portions. In other embodiments, sidewall spacers are formed in the plurality of elongated trenches, and conductive material is placed between the sidewall spacers. Sidewall spacers also may be formed in the portions of the first and/or second elongated regions that are selectively removed prior to placing conductive material therein.
According to other embodiments of the invention, a semiconductor device is fabricated by depositing a lower insulating film and an upper insulating film having line patterns therein on a substrate, forming a mask film in spaces between the line patterns and planarizing the mask film until a surface of the line patterns is exposed. Grooves which extend across the line patterns are formed in the lower insulating film, by patterning the line patterns and the mask films. A spacer is formed on the sidewalls of the grooves and a conductive layer is formed in the grooves between the sidewalls. The conductive layer is covered with a capping film and the capping film is planarized until a surface of the patterned mask film is exposed. Contact holes are formed that are aligned to the conductive layer by selectively removing the mask film between adjacent portions of the conductive layer and the capping film. The lower portions of the contact holes are extended by removing the lower insulating film beneath the contact holes. Contact plugs are formed by forming a conductive substance in the contact holes.
In some embodiments, the mask film comprises a film having a etching selectivity to the upper insulating film and the capping film. For example, the mask film may be a nitride film and the upper insulating film and the capping film may be oxide films.
According to other embodiments of the present invention, there is provided methods for fabricating semiconductor devices comprising forming gate stacks on, and sources/drains in a substrate, covering spaces between the gate stacks with a first insulating film and planarizing the first insulating film, and forming first cell pads connected to respective sources and second cell pads connected to respective drains through the first insulating film. These embodiments further comprise forming a second insulating film on the first insulating film, the first cell pads and the second cell pads, forming a bit line contact plugs contacting the second cell pads through the second insulating film and forming a third insulating film on the second insulating film and the bit line contact plugs. These embodiments further comprise forming line patterns which expose a region where a storage node contact plug is to be formed and is parallel to the gate stacks, by etching the third insulating film, covering spaces between the line patterns with a mask film and planarizing the mask film until a surface of the line patterns is exposed, and forming reverse patterns which define grooves for bit lines, by patterning the line patterns and the mask film at the same time. Finally, these embodiments further comprise forming a first spacer on the sidewalls of the reverse patterns, forming the bit lines by covering spaces between the reverse patterns, where the first spacer is formed, with a conductive layer, covering the bit lines with a capping film which fills spaces between the reverse patterns and planarizing the capping film until the reverse patterns are exposed. Storage node contact holes are formed, which expose the second insulating film, by wet etching the patterned mask film of the resultant structure where the capping film is formed. The lower portions of the storage node contact holes are extended by dry etching the exposed second insulating film, and the storage node contact plugs are formed by filling the storage node contact holes with a conductive substance.
In some embodiments, active regions where the sources and drains are formed are orthogonal to the gate stacks. However, in other embodiments, the active regions may also have a diagonal structure where the active regions are aligned with the gate stacks at an acute angle.
In some embodiments, the mask film is a film having a wet-etching selectivity to the third insulating film, the first spacer, and the capping film. For example, the mask film may be a nitride film and the third insulating film, the first spacer, and the capping film may be oxide films.
After the storage node contact holes, which expose the second insulating film, are formed by wet etching the patterned mask film, some embodiments form a second spacer on the inner walls (sidewalls) of the storage node contact holes. Some embodiments also extend the lower portions of the storage node contact holes by dry etching the exposed second insulating film, using the capping film and the second spacer as etching masks.
After the lower portions of the storage node contact holes are extended, a third spacer may be formed on the inner walls of the extended storage node contact holes, in other embodiments.